1. Field of the Invention
This invention relates generally to optical logic-based computing methods and to devices and systems for practicing such methods. More particularly this invention relates to hybrid optical/electronic methods and arrangements for implementing general digital logic, including combinational logic, sequential logic, and/or mixtures thereof. Specifically, this invention relates to novel architectures and methods for implementing any truth table based logic scheme requiring a combination of both fiber optic and electrically connected processing elements or for implementing any algorithm requiring a combination of both fiber optic and electrically connected processing elements, including one processor or multiple processors operating in parallel.
2. Description of the Related Art
In my U.S. Pat. No. 4,821,222, there are described arrangements and methods for the design of a hybrid optical/electronic system that implements logic or computing functions. The system consists of a programmable hybrid optical/electronic INVERT-OR-INVERT-OR logic array that is functionally equivalent to an AND-OR electronic programmable logic array ("PLA") device with decoders. In the hybrid system, electronic decoders send spatially coded binary input information to a row of optical emitters. A programmable optical crossbar is then employed to perform a row-by-row INVERT-OR operation. Light emerging from the crossbar impinges on a column of optical detectors, and individual detector outputs are subsequently inverted electronically. One or more of the resulting signals are then electronically or optically OR'd together. In the background portion of my U.S. Pat. No. 4,821,222 there is a discussion of prior art deemed generally relevant to the inventions described therein.
In my application Ser. No. 231,718, there is described arrangements and methods for the design of a hybrid optical/electronic system that implements a truth table based noncontending N.times.N or N.times.M crossbar switch with bit-slice reconfigurability. The hybrid optical/electronic architecture for implementing the switch contains one or more sets of emitters, a cross connection array with imbedded logic, and one or more sets of detectors. Four basic variations of the architecture are described that effect the same basic truth table. The first variation employs direct fiber connections within the cross connection array. The second variation employs embedded programmable logic devices within the cross connection array. The third and fourth variations each employ embedded multiplexers within the cross connection array, with the fourth variation having memory elements that enable the crossbar switch to operate synchronously. In the background portion of application Ser. No. 231,718, there is described a series of references which are generally relevant to the inventions described therein.
The architecture and methods of the present invention represent an evolution of the designs presented and discussed in my application Ser. No. 231,718, particularly the design shown in FIG. 2 therein. The architectures and methods are not restricted to programmable logic devices which implement a restricted group of truth tables. Instead, the implementations of the present invention are capable of effecting any combination of sequential and combinational logic. Thus, it should be appreciated that the present invention represents a generalization of the embedded logic in the cross connection array shown in FIG. 2 of application Ser. No. 231,718.
For further background material on the generalization of crossbar switch-based architectures, reference may be had to four additional references. The first such reference is R. Arrathoon, "Logic Based Spatial Light Modulators," Proceedings of the Society of Photo-Optical Instrumentation Engineers, Vol. 881, pp. 230 (Jan. 1988). This paper suggests that it may be possible to extend basic crossbar switch architectures to achieve a more general logic function, but does not describe methods or structures for implementing such generalized systems.
The second reference is by T. Wang, M. Arshad, and R. Arrathoon, "Optically Controlled Fiber Optic Logic Arrays," Proceedings of the Society of Photo-Optical Instrumentation Engineers, Vol. 977, p. 12 (San Diego, Aug. 1988). This paper was delivered on 18 August 1988 after the filing of application Ser. No. 231,718 and discusses my proposed use of the cross connection architecture with embedded logic for applications that are not solely restricted to the implementation of a simple crossbar switch. The paper includes one figure showing that an additional set of input and control bits may be used to increase the flexibility of the cross connection architecture.
The third reference is by R. Arrathoon, "High Fan Factor Architectures for Optical Parallel Processing," Proceedings of the Third Annual IEEE Parallel Processing Symposium (Fullerton, CA, March 1988). This paper provides further information pertaining to the use of the cross connection architecture, embedded logic, and additional set of input and control bits. The design is more fully shown and described in my application Ser. No. 231,718.
A fourth reference which provides a treatment of this general subject area in a manner that is similar to the aforementioned first reference is R. Arrathoon, OPTICAL COMPUTING, Chapter 9, pp. 247-277 (January 1989; Marcel Dekker, New York Publisher).
The four references just mentioned are hereby incorporated herein by reference, since they provide, for those not fully familiar with digital optical computing principles and performance measures, advantages and operating principles useful to a full appreciation of the apparatuses and methods of the present invention. These four references represent the results of my earlier work, and generally describe systems and methods that are relatively narrow in scope and directed towards a limited class of logic operations. Moreover, these four references fail to disclose in any usable detail the specific embodiments and methods described herein for achieving the general purpose functionality of the present invention, as described below.
There has been a growing recognition during the last decade that the limits of electronic digital processing technology are rapidly being approached. In particular, there is a growing awareness in the digital optics computing community that it is essential to mix optics with electronics in order to achieve superior performance in digital computation, particularly for high-speed, high-complexity calculations and for large programs now used or planned for many applications ranging from artificial intelligence, image processing, pattern recognition, to database management, among others. In this regard, there has been a long-standing need for a general purpose optoelectronic architecture which would maximize the advantages achievable with hybrid optoelectronic/digital computing systems. To the best of my knowledge, all previous crossbar systems and related approaches to digital computing failed to merge or arrange electronic components within the cross connection array to maximize the advantages of high optical fan-in and fan-out factors and the global connectivity of the hybrid crossbar architecture illustrated in FIG. 2 of my application Ser. No. 231,718.
The objects of the embodiments of my inventions first described in application Ser. No. 321,718 (and also described here) include the following:
(1) to provide a method and apparatus for a hybrid optical/electronic noncontending NXM crossbar switch that overcomes many of the restrictions of existing crossbar switches in terms of being able to achieve both high data rates and high reconfiguration rates;
(2) to achieve the first object (Object 1) by providing a method and apparatus for implementing a truth table based hybrid optical/electronic noncontending N.times.M crossbar switch with bit-slice reconfigurability;
(3) to provide a method and apparatus for a generalized structure that is capable of implementing a truth table based hybrid optical/electronic noncontending N.times.M crossbar switch with bit-slice reconfigurability;
(4) to provide a method and apparatus for a truth table based hybrid optical/electronic asynchronous noncontending N.times.M crossbar switch that is effected by optoelectronic means through the sequence INVERT-OR-INVERT-OR;
(5) to provide a method and apparatus for a truth table based hybrid optical/electronic asynchronous noncontending N.times.M crossbar switch that is effected by a combination of optoelectronic means and programmable logic devices (PLDs);
(6) to provide a method and apparatus for a truth table based hybrid optical/electronic asynchronous noncontending N.times.M crossbar switch that is effected by a combination of optoelectronic means and multiplexers;
(7) to provide a method and apparatus for a truth table based hybrid optical/electronic synchronous noncontending N.times.M crossbar switch that is effected by a combination of optoelectronic means, multiplexers, and memory elements.
The present invention seeks to add to, generalize and improve upon the embodiments of my invention described in application Ser. No. 231,718. The objects of the present invention may be more specifically described as follows:
(8) to provide a method and apparatus for mixing and merging high optical fan-in and fan-out factors with electronic fan-in and fan-out factors contained within a fiber coupled cross connection array including embedded electronic logic devices in order to implement in a hybrid optical/electronic manner any digital logic scheme requiring combinational and/or sequential logic;
(9) to provide a method and apparatus for implementing any truth table-based logic scheme or, equivalently, any combinational logic based scheme with an array of both fiber optic and electrically connected programmable logic devices (PLDs);
(10) to provide a method and apparatus for implementing any truth table-based logic scheme or, equivalently, any combinational logic based scheme with an array of both fiber optic and electrically connected read only memories (ROMs);
(11) to provide a method and apparatus for implementing any dynamically programmable memory scheme with an array of both fiber optic and electrically connected random access memories (RAMs);
(12) to provide a method and apparatus for implementing any algorithm requiring a combination of both fiber optic and electrically connected processing elements, including one processor or multiple processors operating in parallel;
(13) to provide a method and apparatus for implementing any algorithm and/or truth table requiring a combination of both fiber optic and electrically connected application specific integrated circuits (ASICs) and/or electronic logic elements.
(14) to achieve the Objects 8 through 13 above by utilizing any combination of electronic fan-in and fan-out factors and sequential and/or combinational logic elements embedded within a fiber optically coupled cross connection array in a globally-connected high fan factor architecture.
(15) to achieve the Objects 8 through 14 above by simultaneously processing any or all multiple input arrays of input data bits and/or input control bits and/or input timing bits utilizing any combination of electronic fan-in and fan-out factors and sequential and/or combinational logic elements embedded within a fiber optically coupled generalized cross connection array.